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--- naivety_core [2026/05/13 13:51] – created page for CPU iliketech
+++ naivety_core [2026/05/13 14:20] (current) – Added three operand instructions iliketech
@@ Line 5: / Line 5: @@
 === Overview ===
-This processor is a 16-bit data / address design, with fixed-width instructions. The processor is based around a finite state machine, with most instructions completing in four cycles. Most operations (math, logic) are register-register only and do not support operation with immediates due to limited instruction width. At the moment, the processor does not support flags of any sort. Conditionals are done only via direct register comparison.
+This processor is a big-endian 16-bit data / address design, with fixed-width instructions. The processor is based around a finite state machine, with most instructions completing in four cycles. Most operations (math, logic) are register-register only and do not support operation with immediates due to limited instruction width. At the moment, the processor does not support flags of any sort. Conditionals are done only via direct register comparison.
 === Registers ===
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 | | | |
 | rir | N/A | Instruction register |
+=== Instructions ===
+The processor uses 5-bit opcodes on fixed 16-bit wide instructions, using four instruction formats.
+== Instruction Formats ==
+There are four main instruction formats, shown in the following table. Registers are denoted with <src> and <dst>. Immediate numbers are denoted with <imm> and addresses are denoted with <addr> or <rpc_addr> (for PC-relative addresses).
+^ Format # ^ Bit Number: 15 (MSB) ^ 14 ^ 13 ^ 12 ^ 11 ^ 10 ^ 9 ^ 8 ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 (LSB) ^
+| 0 | opcode ||||| <dst> |||| reserved | <src1> ||| <src2> |||
+| 1 | opcode ||||| <dst> |||| reserved ||| <src> ||||
+| 2 | opcode ||||| <dst> |||| <imm> |||||||
+| 3 | opcode ||||| <rpc_addr> |||||||||||
+Note that format 0 instructions only have 3-bit source register fields due to instruction width limits. This means that while the destination for format 0 instructions can be any register, <src1> is restricted from r0 to r7, and <src2> is restricted to r8 onward.
+== Instruction List ==
+Currently supported instructions are shown in the following table.
+^ Instruction Name ^ Description ^ Opcode ^ Format # ^
+| nop | No operation | 0b00000 | 0 |
+| add | dst <- src1 + src2 | 0b00001 | 0 |
+| sub | dst <- src1 - src2 | 0b00010 | 0 |
+| mul | dst <- src1 * src2 | 0b00011 | 0 |
+| shl | dst <- src1 << src2 | 0b00100 | 0 |
+| shr | dst <- src1 >> src2 | 0b00101 | 0 |
+| and | dst <- src1 & src2 | 0b00110 | 0 |
+| or | dst <- src1 %%|%% src2 | 0b00111 | 0 |
+| xor | dst <- src1 %%^%% src2 | 0b01000 | 0 |
+| jt | rpc <- dst if <src1> == <src2> | 0b01001 | 0 |
+| | | | |