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Naivety Core
This is the custom 16-bit CPU design used in Naivety Project.
Overview
This processor is a big-endian 16-bit data / address design, with fixed-width instructions. The processor is based around a finite state machine, with most instructions completing in four cycles. Most operations (math, logic) are register-register only and do not support operation with immediates due to limited instruction width. At the moment, the processor does not support flags of any sort. Conditionals are done only via direct register comparison.
Registers
The processor has 16x 16-bit wide registers, shown in the following table:
| Register Name | Register Number | Description |
|---|---|---|
| r0 | 0 | General purpose |
| r1 | 1 | |
| r2 | 2 | |
| r3 | 3 | |
| r4 | 4 | |
| r5 | 5 | |
| r6 | 6 | |
| r7 | 7 | |
| r8 | 8 | |
| r9 | 9 | |
| r10 | 10 | |
| r11 | 11 | |
| rpc | 12 | Program counter |
| rsp | 13 | Stack pointer |
| rlr | 14 | Link register |
| rir | N/A | Instruction register |
Instructions
The processor uses 5-bit opcodes on fixed 16-bit wide instructions, using four instruction formats.
Instruction Formats
There are four main instruction formats, shown in the following table. Registers are denoted with <src> and <dst>. Immediate numbers are denoted with <imm> and addresses are denoted with <addr> or <rpc_addr> (for PC-relative addresses).
| Format # | Bit Number: 15 (MSB) | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 (LSB) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | opcode | <dst> | reserved | <src1> | <src2> | |||||||||||
| 1 | opcode | <dst> | reserved | <src> | ||||||||||||
| 2 | opcode | <dst> | <imm> | |||||||||||||
| 3 | opcode | <rpc_addr> | ||||||||||||||