Differences

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--- naivety_core [2026/05/13 14:11] – Added instruction formats. iliketech
+++ naivety_core [2026/05/13 14:20] (current) – Added three operand instructions iliketech
@@ Line 42: / Line 42: @@
 | 2 | opcode ||||| <dst> |||| <imm> |||||||
 | 3 | opcode ||||| <rpc_addr> |||||||||||
+Note that format 0 instructions only have 3-bit source register fields due to instruction width limits. This means that while the destination for format 0 instructions can be any register, <src1> is restricted from r0 to r7, and <src2> is restricted to r8 onward.
+== Instruction List ==
+Currently supported instructions are shown in the following table.
+^ Instruction Name ^ Description ^ Opcode ^ Format # ^
+| nop | No operation | 0b00000 | 0 |
+| add | dst <- src1 + src2 | 0b00001 | 0 |
+| sub | dst <- src1 - src2 | 0b00010 | 0 |
+| mul | dst <- src1 * src2 | 0b00011 | 0 |
+| shl | dst <- src1 << src2 | 0b00100 | 0 |
+| shr | dst <- src1 >> src2 | 0b00101 | 0 |
+| and | dst <- src1 & src2 | 0b00110 | 0 |
+| or | dst <- src1 %%|%% src2 | 0b00111 | 0 |
+| xor | dst <- src1 %%^%% src2 | 0b01000 | 0 |
+| jt | rpc <- dst if <src1> == <src2> | 0b01001 | 0 |
+| | | | |